all repos — nand2tetris @ f75e04cfd808fd4827839ed6751d65227550fe8c

my nand2tetris progress

Re-do RAM512.hdl, RAM4K.hdl, and RAM16K.hdl
x1phosura x1phosura@x1phosura.zone
Sat, 04 Dec 2021 16:10:21 -0800
commit

f75e04cfd808fd4827839ed6751d65227550fe8c

parent

3d86fc3cbea0ab69d0142c3523758d2051a2bd40

M projects/03/a/PROGRESS.mdprojects/03/a/PROGRESS.md

@@ -1,12 +1,10 @@

# Progress -## TODO -RAM64 -RAM8 - ## DONE Bit PC +RAM64 +RAM8 Register
M projects/03/b/PROGRESS.mdprojects/03/b/PROGRESS.md

@@ -1,10 +1,8 @@

# Progress -## TODO +## DONE RAM16K RAM4K RAM512 -## DONE -
M projects/03/b/RAM16K.hdlprojects/03/b/RAM16K.hdl

@@ -15,5 +15,12 @@ IN in[16], load, address[14];

OUT out[16]; PARTS: - // Put your code here: -}+ DMux4Way(in=load, sel=address[12..13], a=load0, b=load1, c=load2, d=load3); + + RAM4K(in=in, load=load0, address=address[0..11], out=ram0); + RAM4K(in=in, load=load1, address=address[0..11], out=ram1); + RAM4K(in=in, load=load2, address=address[0..11], out=ram2); + RAM4K(in=in, load=load3, address=address[0..11], out=ram3); + + Mux4Way16(a=ram0, b=ram1, c=ram2, d=ram3, sel=address[12..13], out=out); +}
M projects/03/b/RAM4K.hdlprojects/03/b/RAM4K.hdl

@@ -15,5 +15,18 @@ IN in[16], load, address[12];

OUT out[16]; PARTS: - // Put your code here: -}+ DMux8Way(in=load, sel=address[9..11], a=load0, b=load1, c=load2, d=load3, + e=load4, f=load5, g=load6, h=load7); + + RAM512(in=in, load=load0, address=address[0..8], out=ram0); + RAM512(in=in, load=load1, address=address[0..8], out=ram1); + RAM512(in=in, load=load2, address=address[0..8], out=ram2); + RAM512(in=in, load=load3, address=address[0..8], out=ram3); + RAM512(in=in, load=load4, address=address[0..8], out=ram4); + RAM512(in=in, load=load5, address=address[0..8], out=ram5); + RAM512(in=in, load=load6, address=address[0..8], out=ram6); + RAM512(in=in, load=load7, address=address[0..8], out=ram7); + + Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7, + sel=address[9..11], out=out); +}
M projects/03/b/RAM512.hdlprojects/03/b/RAM512.hdl

@@ -15,5 +15,18 @@ IN in[16], load, address[9];

OUT out[16]; PARTS: - // Put your code here: -}+ DMux8Way(in=load, sel=address[6..8], a=load0, b=load1, c=load2, d=load3, + e=load4, f=load5, g=load6, h=load7); + + RAM64(in=in, load=load0, address=address[0..5], out=ram0); + RAM64(in=in, load=load1, address=address[0..5], out=ram1); + RAM64(in=in, load=load2, address=address[0..5], out=ram2); + RAM64(in=in, load=load3, address=address[0..5], out=ram3); + RAM64(in=in, load=load4, address=address[0..5], out=ram4); + RAM64(in=in, load=load5, address=address[0..5], out=ram5); + RAM64(in=in, load=load6, address=address[0..5], out=ram6); + RAM64(in=in, load=load7, address=address[0..5], out=ram7); + + Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7, + sel=address[6..8], out=out); +}