// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:
    DMux8Way(in=load, sel=address[9..11], a=load0, b=load1, c=load2, d=load3,
                                          e=load4, f=load5, g=load6, h=load7);

    RAM512(in=in, load=load0, address=address[0..8], out=ram0);
    RAM512(in=in, load=load1, address=address[0..8], out=ram1);
    RAM512(in=in, load=load2, address=address[0..8], out=ram2);
    RAM512(in=in, load=load3, address=address[0..8], out=ram3);
    RAM512(in=in, load=load4, address=address[0..8], out=ram4);
    RAM512(in=in, load=load5, address=address[0..8], out=ram5);
    RAM512(in=in, load=load6, address=address[0..8], out=ram6);
    RAM512(in=in, load=load7, address=address[0..8], out=ram7);

    Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7,
              sel=address[9..11], out=out);
}