M projects/03/a/RAM64.hdl → projects/03/a/RAM64.hdl

@@ -15,5 +15,18 @@ IN in[16], load, address[6];
     OUT out[16];
 
     PARTS:
-    // Put your code here:
-}+    DMux8Way(in=load, sel=address[3..5], a=load0, b=load1, c=load2, d=load3,
+                                   e=load4, f=load5, g=load6, h=load7);
+
+    RAM8(in=in, load=load0, address=address[0..2], out=ram0);
+    RAM8(in=in, load=load1, address=address[0..2], out=ram1);
+    RAM8(in=in, load=load2, address=address[0..2], out=ram2);
+    RAM8(in=in, load=load3, address=address[0..2], out=ram3);
+    RAM8(in=in, load=load4, address=address[0..2], out=ram4);
+    RAM8(in=in, load=load5, address=address[0..2], out=ram5);
+    RAM8(in=in, load=load6, address=address[0..2], out=ram6);
+    RAM8(in=in, load=load7, address=address[0..2], out=ram7);
+
+    Mux8Way16(a=ram0, b=ram1, c=ram2, d=ram3, e=ram4, f=ram5, g=ram6, h=ram7,
+              sel=address[3..5], out=out);
+}

M projects/03/a/RAM8.hdl → projects/03/a/RAM8.hdl

@@ -15,5 +15,18 @@ IN in[16], load, address[3];
     OUT out[16];
 
     PARTS:
-    // Put your code here:
-}+    DMux8Way(in=load, sel=address, a=load0, b=load1, c=load2, d=load3,
+                                   e=load4, f=load5, g=load6, h=load7);
+
+    Register(in=in, load=load0, out=reg0);
+    Register(in=in, load=load1, out=reg1);
+    Register(in=in, load=load2, out=reg2);
+    Register(in=in, load=load3, out=reg3);
+    Register(in=in, load=load4, out=reg4);
+    Register(in=in, load=load5, out=reg5);
+    Register(in=in, load=load6, out=reg6);
+    Register(in=in, load=load7, out=reg7);
+
+    Mux8Way16(a=reg0, b=reg1, c=reg2, d=reg3, e=reg4, f=reg5, g=reg6, h=reg7,
+              sel=address, out=out);
+}