M projects/05/CPU.hdl → projects/05/CPU.hdl

@@ -46,22 +46,22 @@ * A-instruction format: 0xxxxxxxxxxxxxxx
      * - place xxxxxxxxxxxxxxx directly into register A
      *
      * C-instruction format: 111accccccdddjjj (MSB is 1, LSB is j)
-     * bit 0 (j): jump if ALU output is "positive" or if other j-bit is set
-     * bit 1 (j): jump if ALU output is zero or if other j-bit is set
-     * bit 2 (j): jump if ALU output is "negative" or if other j-bit is set
-     * bit 3 (d): ALU output destination is or includes memory (RAM[A])
-     * bit 4 (d): ALU output destination is or includes D register
-     * bit 5 (d): ALU output destination is or includes A register
-     * bit 6 (c): set ALU no, NOT ALU output if 1
-     * bit 7 (c): set ALU f, decide if performing addition or logical AND
-     * bit 8 (c): set ALU ny, decide if ALU x-input should be inverted (NOT)
-     * bit 9 (c): set ALU zy, decide if ALU y-input should be zero
-     * bit 10 (c): set ALU nx, decide if ALU x-input should be inverted (NOT)
-     * bit 11 (c): set ALU zx, decide if ALU x-input should be zero
-     * bit 12 (a): decide if ALU y-input should be inM (memory) or A register
-     * bit 13 (1): always 1 (TODO: try setting to 0 and running)
-     * bit 14 (1): always 1 (TODO: try setting to 0 and running)
-     * bit 15 (1): if 0, then A-type instruction, if 1, then C-type instruction
+     *   bit 0 (j): jump if ALU output is "positive" or if other j-bit is set
+     *   bit 1 (j): jump if ALU output is zero or if other j-bit is set
+     *   bit 2 (j): jump if ALU output is "negative" or if other j-bit is set
+     *   bit 3 (d): ALU output destination is or includes memory (RAM[A])
+     *   bit 4 (d): ALU output destination is or includes D register
+     *   bit 5 (d): ALU output destination is or includes A register
+     *   bit 6 (c): set ALU no, NOT ALU output if 1
+     *   bit 7 (c): set ALU f, decide if performing addition or logical AND
+     *   bit 8 (c): set ALU ny, decide if ALU x-input should be inverted (NOT)
+     *   bit 9 (c): set ALU zy, decide if ALU y-input should be zero
+     *   bit 10 (c): set ALU nx, decide if ALU x-input should be inverted (NOT)
+     *   bit 11 (c): set ALU zx, decide if ALU x-input should be zero
+     *   bit 12 (a): decide if ALU y-input should be inM (memory) or A register
+     *   bit 13 (1): always 1 (TODO: try setting to 0 and running)
+     *   bit 14 (1): always 1 (TODO: try setting to 0 and running)
+     *   bit 15 (1): A-type instruction if 0, C-type instruction if 1
      */
     Mux16(a=instruction, b=alu-out, sel=instruction[15], out=val-set-a);
 
@@ -69,22 +69,8 @@ Not(in=instruction[15], out=not-instr-MSB);
     Or(a=not-instr-MSB, b=instruction[5], out=load-a);
     ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);
 
-    /*
-    Note: this makes it fail comparison at line 9 instead of 13 (wonder why...)
-        // figured it out: this OR should be an XOR, but it might also need to be a
-        // bit more complicated...
-        Not(in=inM[15], out=is-a-instr);
-        And(a=instruction[15], b=instruction[5], out=c-instr-and-m-dest);
-        Xor(a=is-a-instr, b=c-instr-and-m-dest, out=load-a);
-        ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);
-    */
-
-    //TODO: fix that the Or() means an A-instruction can still load
-
-    // Logic: if not jump (set PC=A), then inc. Vice-versa, hence the Not()
-    And(a=jump-or-not, b=instruction[15], out=jump-if-c-instr);
-    Not(in=jump-if-c-instr, out=not-jump-if-c-instr);
-    PC(in=a-reg-out, load=jump-if-c-instr, inc=not-jump-if-c-instr, reset=reset, out[0..14]=pc);
+    PC(in=a-reg-out, load=jump-if-c-instr, inc=not-jump-if-c-instr, 
+                                           reset=reset, out[0..14]=pc);
 
     Mux16(a=a-reg-out, b=inM, sel=instruction[12], out=a-or-m);
 
@@ -94,34 +80,25 @@ f=instruction[7], no=instruction[6],
                                out=alu-out, out=outM,
                                zr=alu-zr, ng=alu-ng);
 
+    DRegister(in=alu-out, load=instruction[4], out=d-reg-out);
+
     // if a C-instruction (MSB==1) AND RAM[A] is a destination, then writeM
     And(a=instruction[15], b=instruction[3], out=writeM);
 
-    //"jump-if" module between ALU and PC
-    // (TODO: simplify, possibly using De Morgan's Law)
-
-        // TODO: actually, I think I found a new problem: I think I need to use
-        // AND instead of XOR...
-    //----------------------------------
+    // "jump-if" module between ALU and PC
     Or(a=alu-zr, b=alu-ng, out=j-or-out);
     Not(in=j-or-out, out=nor-out);
-
     // handle bit 0 (j1), jump if positive
-    Xor(a=nor-out, b=instruction[0], out=xor1);
-    Not(in=xor1, out=jump-positive);
-
+    And(a=nor-out, b=instruction[0], out=jump-positive);
     // handle bit 1 (j2), jump if zero
-    Xor(a=alu-zr, b=instruction[1], out=xor2);
-    Not(in=xor2, out=jump-zero);
-
+    And(a=alu-zr, b=instruction[1], out=jump-zero);
     // handle bit 2 (j3), jump if negative
-    Xor(a=alu-ng, b=instruction[2], out=xor3);
-    Not(in=xor3, out=jump-negative);
-
+    And(a=alu-ng, b=instruction[2], out=jump-negative);
     // basically a 3-way AND
-    And(a=jump-positive, b=jump-zero, out=and1);
-    And(a=and1, b=jump-negative, out=jump-or-not);
-    //----------------------------------
+    Or(a=jump-positive, b=jump-zero, out=or1);
+    Or(a=or1, b=jump-negative, out=jump-or-not);
 
-    DRegister(in=alu-out, load=instruction[4], out=d-reg-out);
+    // Logic: if not jump (set PC=A), then inc. Vice-versa, hence the Not()
+    And(a=jump-or-not, b=instruction[15], out=jump-if-c-instr);
+    Not(in=jump-if-c-instr, out=not-jump-if-c-instr);
 }