M projects/05/CPU.hdl → projects/05/CPU.hdl

@@ -65,25 +65,43 @@ * bit 15 (1): if 0, then A-type instruction, if 1, then C-type instruction
      */
     Mux16(a=instruction, b=alu-out, sel=instruction[15], out=val-set-a);
 
-    Not(in=inM[15], out=not-inM-MSB);
-    Or(a=not-inM-MSB, b=instruction[5], out=load-a);
+    Not(in=instruction[15], out=not-instr-MSB);
+    Or(a=not-instr-MSB, b=instruction[5], out=load-a);
     ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);
+
+    /*
+    Note: this makes it fail comparison at line 9 instead of 13 (wonder why...)
+        // figured it out: this OR should be an XOR, but it might also need to be a
+        // bit more complicated...
+        Not(in=inM[15], out=is-a-instr);
+        And(a=instruction[15], b=instruction[5], out=c-instr-and-m-dest);
+        Xor(a=is-a-instr, b=c-instr-and-m-dest, out=load-a);
+        ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);
+    */
+
+    //TODO: fix that the Or() means an A-instruction can still load
 
     // Logic: if not jump (set PC=A), then inc. Vice-versa, hence the Not()
-    Not(in=jump-or-not, out=not-jump-or-not);
-    // TODO: PC(out=) is 16 bits, but CPU(pc=) is 15 bits, will need to change
-    //     TODO: check errata
-    PC(in=a-reg-out, load=jump-or-not, inc=not-jump-or-not, reset=reset, out[0..14]=pc);
+    And(a=jump-or-not, b=instruction[15], out=jump-if-c-instr);
+    Not(in=jump-if-c-instr, out=not-jump-if-c-instr);
+    PC(in=a-reg-out, load=jump-if-c-instr, inc=not-jump-if-c-instr, reset=reset, out[0..14]=pc);
 
     Mux16(a=a-reg-out, b=inM, sel=instruction[12], out=a-or-m);
 
     ALU(x=d-reg-out, y=a-or-m, zx=instruction[11], nx=instruction[10],
                                zy=instruction[9], ny=instruction[8],
-                               f=instruction[7], no=instruction[6], out=alu-out,
+                               f=instruction[7], no=instruction[6],
+                               out=alu-out, out=outM,
                                zr=alu-zr, ng=alu-ng);
 
+    // if a C-instruction (MSB==1) AND RAM[A] is a destination, then writeM
+    And(a=instruction[15], b=instruction[3], out=writeM);
+
     //"jump-if" module between ALU and PC
     // (TODO: simplify, possibly using De Morgan's Law)
+
+        // TODO: actually, I think I found a new problem: I think I need to use
+        // AND instead of XOR...
     //----------------------------------
     Or(a=alu-zr, b=alu-ng, out=j-or-out);
     Not(in=j-or-out, out=nor-out);