M projects/05/CPU.hdl → projects/05/CPU.hdl

@@ -40,4 +40,70 @@ pc[15];          // address of next instruction
 
     PARTS:
     // Put your code here:
-}+    /* Instruction bit explanation
+     *
+     * A-instruction format: 0xxxxxxxxxxxxxxx
+     * - place xxxxxxxxxxxxxxx directly into register A
+     *
+     * C-instruction format: 111accccccdddjjj (MSB is 1, LSB is j)
+     * bit 0 (j): jump if ALU output is "positive" or if other j-bit is set
+     * bit 1 (j): jump if ALU output is zero or if other j-bit is set
+     * bit 2 (j): jump if ALU output is "negative" or if other j-bit is set
+     * bit 3 (d): ALU output destination is or includes memory (RAM[A])
+     * bit 4 (d): ALU output destination is or includes D register
+     * bit 5 (d): ALU output destination is or includes A register
+     * bit 6 (c): set ALU no, NOT ALU output if 1
+     * bit 7 (c): set ALU f, decide if performing addition or logical AND
+     * bit 8 (c): set ALU ny, decide if ALU x-input should be inverted (NOT)
+     * bit 9 (c): set ALU zy, decide if ALU y-input should be zero
+     * bit 10 (c): set ALU nx, decide if ALU x-input should be inverted (NOT)
+     * bit 11 (c): set ALU zx, decide if ALU x-input should be zero
+     * bit 12 (a): decide if ALU y-input should be inM (memory) or A register
+     * bit 13 (1): always 1 (TODO: try setting to 0 and running)
+     * bit 14 (1): always 1 (TODO: try setting to 0 and running)
+     * bit 15 (1): if 0, then A-type instruction, if 1, then C-type instruction
+     */
+    Mux16(a=instruction, b=alu-out, sel=instruction[15], out=val-set-a);
+
+    Not(in=inM[15], out=not-inM-MSB);
+    Or(a=not-inM-MSB, b=instruction[5], out=load-a);
+    ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);
+
+    // Logic: if not jump (set PC=A), then inc. Vice-versa, hence the Not()
+    Not(in=jump-or-not, out=not-jump-or-not);
+    // TODO: PC(out=) is 16 bits, but CPU(pc=) is 15 bits, will need to change
+    //     TODO: check errata
+    PC(in=a-reg-out, load=jump-or-not, inc=not-jump-or-not, reset=reset, out[0..14]=pc);
+
+    Mux16(a=a-reg-out, b=inM, sel=instruction[12], out=a-or-m);
+
+    ALU(x=d-reg-out, y=a-or-m, zx=instruction[11], nx=instruction[10],
+                               zy=instruction[9], ny=instruction[8],
+                               f=instruction[7], no=instruction[6], out=alu-out,
+                               zr=alu-zr, ng=alu-ng);
+
+    //"jump-if" module between ALU and PC
+    // (TODO: simplify, possibly using De Morgan's Law)
+    //----------------------------------
+    Or(a=alu-zr, b=alu-ng, out=j-or-out);
+    Not(in=j-or-out, out=nor-out);
+
+    // handle bit 0 (j1), jump if positive
+    Xor(a=nor-out, b=instruction[0], out=xor1);
+    Not(in=xor1, out=jump-positive);
+
+    // handle bit 1 (j2), jump if zero
+    Xor(a=alu-zr, b=instruction[1], out=xor2);
+    Not(in=xor2, out=jump-zero);
+
+    // handle bit 2 (j3), jump if negative
+    Xor(a=alu-ng, b=instruction[2], out=xor3);
+    Not(in=xor3, out=jump-negative);
+
+    // basically a 3-way AND
+    And(a=jump-positive, b=jump-zero, out=and1);
+    And(a=and1, b=jump-negative, out=jump-or-not);
+    //----------------------------------
+
+    DRegister(in=alu-out, load=instruction[4], out=d-reg-out);
+}