// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in 
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM==0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time step. If reset==1 then the 
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // Put your code here:
    /* Instruction bit explanation
     *
     * A-instruction format: 0xxxxxxxxxxxxxxx
     * - place xxxxxxxxxxxxxxx directly into register A
     *
     * C-instruction format: 111accccccdddjjj (MSB is 1, LSB is j)
     * bit 0 (j): jump if ALU output is "positive" or if other j-bit is set
     * bit 1 (j): jump if ALU output is zero or if other j-bit is set
     * bit 2 (j): jump if ALU output is "negative" or if other j-bit is set
     * bit 3 (d): ALU output destination is or includes memory (RAM[A])
     * bit 4 (d): ALU output destination is or includes D register
     * bit 5 (d): ALU output destination is or includes A register
     * bit 6 (c): set ALU no, NOT ALU output if 1
     * bit 7 (c): set ALU f, decide if performing addition or logical AND
     * bit 8 (c): set ALU ny, decide if ALU x-input should be inverted (NOT)
     * bit 9 (c): set ALU zy, decide if ALU y-input should be zero
     * bit 10 (c): set ALU nx, decide if ALU x-input should be inverted (NOT)
     * bit 11 (c): set ALU zx, decide if ALU x-input should be zero
     * bit 12 (a): decide if ALU y-input should be inM (memory) or A register
     * bit 13 (1): always 1 (TODO: try setting to 0 and running)
     * bit 14 (1): always 1 (TODO: try setting to 0 and running)
     * bit 15 (1): if 0, then A-type instruction, if 1, then C-type instruction
     */
    Mux16(a=instruction, b=alu-out, sel=instruction[15], out=val-set-a);

    Not(in=instruction[15], out=not-instr-MSB);
    Or(a=not-instr-MSB, b=instruction[5], out=load-a);
    ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);

    /*
    Note: this makes it fail comparison at line 9 instead of 13 (wonder why...)
        // figured it out: this OR should be an XOR, but it might also need to be a
        // bit more complicated...
        Not(in=inM[15], out=is-a-instr);
        And(a=instruction[15], b=instruction[5], out=c-instr-and-m-dest);
        Xor(a=is-a-instr, b=c-instr-and-m-dest, out=load-a);
        ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);
    */

    //TODO: fix that the Or() means an A-instruction can still load

    // Logic: if not jump (set PC=A), then inc. Vice-versa, hence the Not()
    And(a=jump-or-not, b=instruction[15], out=jump-if-c-instr);
    Not(in=jump-if-c-instr, out=not-jump-if-c-instr);
    PC(in=a-reg-out, load=jump-if-c-instr, inc=not-jump-if-c-instr, reset=reset, out[0..14]=pc);

    Mux16(a=a-reg-out, b=inM, sel=instruction[12], out=a-or-m);

    ALU(x=d-reg-out, y=a-or-m, zx=instruction[11], nx=instruction[10],
                               zy=instruction[9], ny=instruction[8],
                               f=instruction[7], no=instruction[6],
                               out=alu-out, out=outM,
                               zr=alu-zr, ng=alu-ng);

    // if a C-instruction (MSB==1) AND RAM[A] is a destination, then writeM
    And(a=instruction[15], b=instruction[3], out=writeM);

    //"jump-if" module between ALU and PC
    // (TODO: simplify, possibly using De Morgan's Law)

        // TODO: actually, I think I found a new problem: I think I need to use
        // AND instead of XOR...
    //----------------------------------
    Or(a=alu-zr, b=alu-ng, out=j-or-out);
    Not(in=j-or-out, out=nor-out);

    // handle bit 0 (j1), jump if positive
    Xor(a=nor-out, b=instruction[0], out=xor1);
    Not(in=xor1, out=jump-positive);

    // handle bit 1 (j2), jump if zero
    Xor(a=alu-zr, b=instruction[1], out=xor2);
    Not(in=xor2, out=jump-zero);

    // handle bit 2 (j3), jump if negative
    Xor(a=alu-ng, b=instruction[2], out=xor3);
    Not(in=xor3, out=jump-negative);

    // basically a 3-way AND
    And(a=jump-positive, b=jump-zero, out=and1);
    And(a=and1, b=jump-negative, out=jump-or-not);
    //----------------------------------

    DRegister(in=alu-out, load=instruction[4], out=d-reg-out);
}