M projects/05/CPU.hdl → projects/05/CPU.hdl

@@ -65,6 +65,7 @@ *   bit 15 (1): A-type instruction if 0, C-type instruction if 1
      */
     Mux16(a=instruction, b=alu-out, sel=instruction[15], out=val-set-a);
 
+    // if NOT A-type instruction OR destination A register
     Not(in=instruction[15], out=not-instr-MSB);
     Or(a=not-instr-MSB, b=instruction[5], out=load-a);
     ARegister(in=val-set-a, load=load-a, out=a-reg-out, out[0..14]=addressM);
@@ -80,7 +81,9 @@ f=instruction[7], no=instruction[6],
                                out=alu-out, out=outM,
                                zr=alu-zr, ng=alu-ng);
 
-    DRegister(in=alu-out, load=instruction[4], out=d-reg-out);
+    // if C-type instruction AND destination D register
+    And(a=instruction[15], b=instruction[4], out=load-d);
+    DRegister(in=alu-out, load=load-d, out=d-reg-out);
 
     // if a C-instruction (MSB==1) AND RAM[A] is a destination, then writeM
     And(a=instruction[15], b=instruction[3], out=writeM);